Various types of circuitized substrates having plated, e.g., electroplated, circuitry thereon or as part thereof are known in the art, including those made and sold by the assignee of this invention. Examples of such substrates, including those of the integrated circuit (or semiconductor chip or device) category and various methods of manufacturing same are described in the following U.S. Letters Patents:
4,865,873Cole, Jr., et al4,877,644Wu et al5,018,164Brewer et al5,310,624Ehrlich5,264,108Mayer et al5,843,806Tsai5,968,847Ye et al6,488,862 B1Ye et al
One particularly attractive circuitized substrate made and sold by the assignee of the invention is called the HyperBGA chip carrier, which includes a laminate substrate-conductor layer structure on which is positioned one or more semiconductor chips. (HyperBGA is a registered trademark of Endicott Interconnect Technologies, Inc.). The carrier is then positione on and electrically coupled to a printed circuit board (PCB) or other suitable substrate and this entire subassembly in then utilized in an electronic assembly such as a personal computer, server, etc. The latter assemblies are often referred to generically in the industry as “information handling systems”.
Examples of such a chip carrier are defined in filed application Ser. No. 10/394,135 and Ser. No. 10/394,107, both filed Mar. 24, 2003 and assigned to the same assignee as the invention.
Yet another chip carrier made and sold by the assignee of this invention is referred to as a wirebond, laminate chip carrier in which the chip is coupled to surface conductors by wirebonds. In the typical HyperBGA carrier, the chip is coupled to the surface conductors on the substrate by solder ball connections.
In the formation of such laminate substrates, if electroplating is utilized, a “commoning bar” is typically used as part of the circuitry to form a common connection to the desired circuit elements, e.g., pads or lines, being plated up with the desired metal, e.g., copper. Such a process requires the use of various masking steps in combination with photolithographic processing, both adding cost to the final product.
The present invention overcomes the aforementioned disadvantages associated with such substrate manufacture (applicable not only to chip carriers but also to larger PCBs and the like substrates) by eliminating these additional steps while still providing an efficient, less complex process that will still assure an excellent final substrate product. Because of this, the resulting assembly using same will also inherit the beneficial advantages, especially reduced cost, thereof. It is believed that a method of making a circuitized substrate that will provide such advantages will constitute a significant advancement in the art, as will the resulting substrate and the information handling systems which utilize said product.